Digital electronic circuits are used in virtuially every modern electronic system, such as computers, watches and telephones. Under continuous pressure from users for increased functionality from electronic systems, designers and manufacturers of digital electronic circuits constantly strive to reduce the size and increase the performance of their circuits. Even modest gains in the density and/or performance of a circuit become substantial if the circuit is repeated many times within a system.
Traditionally, digital logic functions have been implemented with a plurality of discrete logic circuits or gates including AND gates, OR gates, NAND gates, NOR gates, etc., each constructed of several transistors. Subsequently, it was discovered that certain special purpose digital circuits such as multiplexers could be used to implement digital logic functions using fewer transistors than with discrete gates. In addition, improved multiplexers were developed which used even fewer transistors. These multiplexers, commonly known as "Transmission Gate" multiplexers, are described in my prior U.S. Pat. Nos. 5,040,139, 5,162,666, 5,200,907, and 5,548,231, the disclosures of which are herein incorporated by reference.
FIG. 1 shows an exemplary 4:1 transmission gate multiplexer 10 connected to an output driver 11. Transmission gate multiplexer 10 includes three 2:1 transmission gate multiplexers 12a-c connected in a serial cascading or hierarchical configuration, as described in my U.S. Pat. No. 5,162,666. The 2:1 transmission gate multiplexer (hereinafter referred to as a TGM) is the basic building block of larger transmission gate multiplexer systems. Each TGM is configured to receive two input signals I.sub.i and I.sub.i+1, and a control signal S.sub.i. The TGM selects one of the two input signals based on the logic value of control signal S.sub.i. The selected input signal is transmitted to the output of the TGM, while the input signal not selected is blocked. The output of each TGM is connected to one of the inputs of the next higher TGM until final TGM 12c is reached. Thus, one of N input signals can be selected for transmission using N-1 TGM's connected in a hierarchical arrangement. The output of final TGM 12c typically is connected to an output driver 11 which is adapted to charge and discharge relatively large capacitive loads. The signal from output driver 11 is designated Q in FIG. 1.
FIG. 2 shows the construction of a typical TGM and output driver using Complimentary Metal Oxide Semiconductor (CMOS) technology. TGM 12c includes two transmission gate pairs 16, each having one P-channel transistor 18 with a drain 20, a source 22, and a gate 24, and one N-channel transistor 26 with a drain 28, a source 30, and a gate 32. The drain of each P-channel transistor is connected to the source of the corresponding N-channel transistor. Similarly, the source of each P-channel transistor is connected to the drain of the corresponding N-channel transistor.
The P-channel transistor will transmit a signal between the source and drain only when a negative voltage is applied to the gate with respect to the source. In contrast, the N-channel transistor will transmit a signal between the source and drain only when a positive voltage is applied to the gate with respect to the source. Thus, if opposite voltages are applied to the gates of the P-channel and N-channel transistor simultaneously, both transistors will either be switched "on" or switched "off."
A select signal S.sub.i is connected to the P-channel transistor of the first transmission gate pair and the N-channel transistor of the second transmission gate pair. The select signal is also passed through an inverter 34 which produces a signal opposite the select signal. Inverter 34 may be a conventional CMOS transistor pair connected between VDD and Ground, as is described in more detail below. The inverted select signal is connected to the N-channel transistor of the first transmission gate pair and the P-channel transistor of the second transmission gate pair. As a result, when S.sub.i is low (also referred to herein as "Ground" or "logical 0") the input signal I.sub.i connected to the first transmission gate pair is transmitted to the output node 36 of the TGM. Conversely, when S.sub.i is high (also referred to herein as "VDD" or "logical 1") the input signal I.sub.i+1, connected to the second transmission gate pair is transmitted to output node 36.
The transmitted signal at output node 36 is connected to an output driver 11. Similar to inverter 34, the exemplary output driver shown in FIG. 2 is in the form of a CMOS inverter having one P-channel transistor 38 and one N-channel transistor 40. The P-channel transistor is connected between VDD and the N-channel transistor, while the N-channel transistor is connected between Ground and the P-channel transistor. The output node of the TGM is connected to the gates of transistors 38 and 40. The inverter output node 42 produces a signal Q opposite the transmitted signal. Transistors 38 and 40 are appropriately sized to drive the expected output load. As can be seen from FIG. 2, the combination of the final TGM and output driver uses eight transistors. If desired, the output driver may include two inverters connected in series to produce the transmitted signal without inversion.
In addition to the exemplary multiplexer described above, there are many other multiplexer configurations well known in the art. For example an N:1 multiplexer can be formed by arranging a plurality of TGM's in a tree-type hierarchical structure as is known in the art. As another example, multiplexers can be formed using traditional logic gates instead of transmission gates. In view of the wide-spread use of multiplexers to implement digital logic functions, an increase in multiplexer performance or a reduction in the number of transistors needed to form a multiplexer would constitute a substantial improvement over existing technology.